1. Field of the Invention
The system of the present invention is related to the field of bus arbitration within computer systems. Specifically, the system of the present invention relates to a bus arbitration architecture incorporating mechanisms to detect and resolve arbitration deadlock conditions created by substantially contemporaneous bus control requests issued by multiple masters.
2. Art Background
In a computer system, shared resources are commonly utilized to transfer data. One commonly used shared resource is a bus serving as a communication link between subsystems (e.g., processors) in a computer system. Generally, multiple devices may be coupled to the bus, wherein one device may transmit control signals or data to other devices coupled to the same bus. A common constraint in bus communications is that more than one device cannot transfer data on the same bus at the same time, because the data may be distorted. In order to maintain order of data transactions on the bus, one device is assigned to be a bus master which initiates read or write transaction to some other device which acts as a slave for that transaction. An arbitration scheme is utilized to determine which master gets control of the bus, determining the priority of the masters seeking control of the bus. There are generally two types of arbiters, serial and parallel. For specific information regarding bus arbiters, see, Stablings, Computer Orgranization and Architecture (1990), pp. 84-90.
More sophisticated computer systems may have multiple interconnected buses and multiple masters coupled to each bus. In a multiple bus multiple master computer system, a master may initiate a data transfer operation to a slave on a first bus, while another master may transfer data to a second slave on a second bus. A bus coupler is typically used to assist in routing data and control signals between the buses, and to determine which master should control which bus. Typically, a coupler includes at least one bus protocol unit, a data translation and buffering device, and at least one bus arbiter. The bus protocol is implemented through an interface which accommodated bus control signals. The data translation and buffering device assures that data are received and sent at the appropriate data rate, because the master may send data from one bus at one data rate and the slave on another bus may receive data at a different data rate. The bus arbiter allocates time for the master on the bus and grants control of the bus to one master at a time.
Referring to FIG. 1, a multiple bus system is illustrated. In FIG. 1, the multiple bus system includes two buses 51 and 57 interconnected via bus coupler 56. Masters 50 and 52 are connected to bus 51, and bus 57 interconnects master 58 and slaves 55 and 59. In the multiple bus system illustrated in FIG. 1, a "live" or continuing arbitration deadlock situation may arise when two masters coupled to two different buses attempt to access the same slave. That is, two masters seeking control of two different buses may create a continual, or "live", deadlock condition for the arbiters of the respective buses, wherein the masters requesting the bus connecting the target slave in a complementary synchronous fashion cause bus coupler 56 to deny access to the target slave by both masters. For example, master 50 coupled to bus 51 may gain control of bus 51 and bus 57 to access slave 59 to initiate a read or write transaction. While slave 59 performs the read or write transaction, slave 59 issues a "relinquish and retry" signal to master 50 if the transaction exceeds a predetermined amount of time. The "relinquish and retry" signal issued by slave 59 causes master 50 to temporarily disconnect from the access path, i.e., release control of bus 51 and bus 57, and retry access to slave 59 again later. Thus, both bus 51 and bus 57 are freed so that other devices can communicate over the bus while slave 59 completes the assigned transaction in the "background". For example, master 52 may access slave 55 while slave 59 is busy with the assigned transaction. Further, bus couple 56 designates master 50 to be the only device which may reselect slave 59. Therefore, no other master can access slave 59 prior to master 50 reaccessing slave 59. However, before master 50 has an opportunity to retry access to slave 59, master 58 gains control of bus 57 and attempts to initiate a transaction with slave 59. Because slave 59 is allocated to master 50, bus coupler 56 will deny access to master 58, bus coupler 56 permitting access only by master 50 to "clear" the pending relinquish and retry "condition" pursuant to the issued "relinquish and retry" signal
When master 50 reinitiates the process to access the slave 59, the arbiter for bus 57 again denies master 50 control of bus 57 because bus 57 is currently engaged by master 58. Master 50 is instructed to "backoff" by the arbiter for bus 57, i.e., stop requesting control of bus 57, and subsequently retry to obtain control of bus 57. Furthermore, although the arbiter for bus 57 has allowed master 58 to control bus 57, master 58 will not be permitted to access slave 59 because master 50 was issued the "relinquish and retry" signal by slave 59. Recall that bus coupler 56 will only accept an access request from master 50 to clear the relinquish and retry signal issued by slave 59. Thus, master 58 will be instructed to "backoff" from slave 59, i.e., stop requesting access to slave 59, and wait until master 50 has accessed slave 59. Hence, the "live" deadlock situation arises when both masters 50 and 58 contemporaneously seek control of bus 57 and access to slave 59, wherein both masters 50 and 58 are told to backoff and try again at a later time.
As will be described in more detail below, the present invention permits potential arbitration deadlock conditions to be detected and subsequently resolved by providing a free-running timer to introduce a random time "offset" to bus requests issued by multiple masters. The random time offset permits bus requests made by one master to be masked, so that a second master may access the slave and clear the previous operation.